Deep-submicron scaling required for VLSI systems dominates design considerations in the microelectronics industry. As the length of the gate electrode is scaled down, the source and drain junctions must be scaled down accordingly to suppress the so-called short channel effects (SCE) that degrade performance of miniaturized devices. A major problem related to complementary metal oxide silicon (CMOS) scaling is the undesirable increase in parasitic resistance. As the source/drain junction depth and polycrystalline silicon line width are scaled into the deep-submicron range, contact resistance becomes more significant and needs to be reduced.
The principle way of reducing contact resistances between polysilicon gates and source/drain regions and interconnect lines is to form metal silicides atop the source/drain regions and the gate electrodes. Among the most common metal silicide materials are nickel silicide and cobalt silicide, typically formed by salicide (self-aligned silicide) processes. In a salicide process, a thin layer of metal is blanket deposited over a semiconductor wafer having exposed source/drain and gate electrode regions. The wafer is then subjected to one or more annealing steps. This annealing process causes the metal to selectively react with the exposed silicon of the source/drain regions and the gate electrode, thereby forming a metal silicide. The process is referred to as a self-aligned silicidation process because the silicide layer is formed only where the metal material directly contacts the silicon source/drain regions and the polycrystalline silicon (polysilicon) gate electrode.
In conventional silicidation processes, if gate electrodes are formed of polysilicon, silicides are also formed on the gate electrodes. Various customized designs may be performed to meet different requirements. For example, fully silicided (FUSI) gates may be formed to eliminate poly depletion effects, which are caused by polysilicon's relatively low charge-supplying ability. NMOS devices and PMOS devices may also have silicided gates with different work functions. These customized designs require that source/drain silicide regions be formed separately from the formation of gate silicide regions.
FIG. 1 illustrates a cross-sectional view in the manufacturing of a conventional MOS device. After the formation of source/drain regions 14 and source/drain silicide regions 12, a contact etch stop layer (CESL) 10 is blanket formed. In order to silicide polysilicon gate 4, a chemical mechanical polish (CMP) is performed to remove structures over polysilicon gate 4, including the portion of CESL 10 over polysilicon gate 4. Polysilicon gate 4 is then silicided using a conventional salicide process.
FIG. 2 is a top view of the structure shown in FIG. 1. It is noted that due to the CMP process, CESL 10 is separated into two portions, a portion over the source region and a portion over the drain region. This significantly reduces the stress applied by CESL 10 to the channel region of the resulting MOS device. A further problem is that since the portion of CESL 10 over polysilicon gate 4 is removed, in a subsequent process for forming contact openings in an inter-layer dielectric, there is no etch stop layer to stop the etching process. A portion of the gate silicide region, and possibly polysilicon gate 4, may be etched. This will result in the increase in contact resistance.
Accordingly, what is needed in the art is a new method and structure that may incorporate separate gate and source/drain silicide formation processes to take advantage of the benefits associated with customized gate and source/drain silicide regions while at the same time overcoming the deficiencies of the prior art.